20260219_H-201_Cheruliyil.PDF

1、Archana Cheruliyil-Alphawave Semi,a Qualcomm Company Chiplets Everywhere:Why Robust D2D at 64G Matters for Scalable Architectures2Communication happens on the chip shorelineMonolithic die performance is maxed outTrends in Silicon,Packaging,and InterconnectSiliconSingle reticleMulti-die,2.5D ChipletM

2、ulti-die,3D ChipletNext gen high count multi-dieInterposerNA3.3X reticle 5X reticleNASubstrateOrganicOrganic,70 mmOrganic,120 mmOrganic/PCBD2D IONAUp to 36G6G 3DIO64G+Power deliveryTop side/LateralBottom side/LateralBottom side/Vertical PDNVertical PDNPower of UCIe:Alphawave Semi Chiplet Building Bl

3、ocksCOMPUTE TO COMPUTECOMPUTE TO MEMORYCOMPUTE TO ELECTRICAL IO/OPTICAL IOTopologyPHYUCIe Standard Package UCIe Advanced Package UCIe Standard Package UCIe Advanced Package UCIe Standard Package UCIe Advanced Package Data Rates32Gbps/64Gbps 32Gbps32Gbps/64Gbps ProtocolUCIe Streaming UCIe Streaming t

4、o cHBMUCIe Streaming to DDR ChipletUCIe Streaming or RetimerCompute chipletsCompute chipletscHBMASICASICDSPDSPAlphawave UCIe Building Blocks available today in all major Foundries in Multiple Technology Nodes Compute to MemoryNext-Gen Memory Is Here:A Deep Dive into HBM4 HBM4JEDEC HBM4Traditional wo

5、rkflowHigh volumeCustom HBM4Logic DRAM processCustom Logic DieDatacenterArtificialIntelligenceEnd MarketsIOs doubling to 2048 bitsBackward(Electrical and Protocol)compatible to HBM3 with minor changesCustom memory base die with D2D interface implementation to enable higher bandwidth for AI applicati

6、onThe Power of D2D:Compute to MemoryAI workloads require custom implementation of memory access and competitive PPA tailored to individual workload requirements.ParameterHBM4 JEDECCustom HBM4 using UCIe 32GCustom HBM4 using UCIe 64GData Width#20486464Data Rate