20260218_E-103_Hosseini.PDF

1、Chiplet SummitChiplet SummitFebruary 17February 17-19,2026,Santa Clara,CA,USA19,2026,Santa Clara,CA,USAChiplet Packaging to Scale AIChiplet Packaging to Scale AIAditya Vaidya,Si-Pkg Arch and Customer Enabling LKaveh Hosseini PhD,Principal EFebruary 18,2026Acknowledgements:R.Mahajan,several Intel tea

2、m members Chiplet Summit 2026,Aditya Vaidya2 What is AI scaling and what is needed to keep up with it Basics of an AI chip and how to scale it Challenges and opportunities Warpage Power Delivery Thermal challenges Yield and Redundancy ConclusionOutlineChiplet Summit 2026,Aditya Vaidya3AI scalingScal

3、ing requires more data used for training,more model parameters and faster compute(1)Amount of FLOP/s per$doubles every 2.5 years(2)AI scaling requires more compute and memory which in turn requires more Si packed on the packageHeterogeneous Si and memory integration is cost effective and scalable wa

4、y to achieve thisTrend of substrate and silicon area for AI packagesChiplet Summit 2026,Aditya Vaidya4Chiplets in AI package and its scalabilityHigh BW communication needed between the different elements of the unit cellOff package communication handled via IO dieScaling for the AI chip will require

5、 multiple such unit cells placed on a packageWafer scale packaging is first attempt at scaling but is limited to wafer sizeIntels EMIB-T based architecture allows an elegant and sustained scaling solutionSource:Intel on YoutubeAI scaling using EMIB-T to achieve 10 x reticle complexBlow up view of Te

6、sla Dojo AI training tile(3)Unit CellxPU=Compute chipletHBM=Memory chipletIO=Data in and out of packagexPUHBMHBMIONVIDIA Blackwell GPU(4)AMD MI300(5)Intel Gaudi 3(6)All Si to Si solution via EMIBEMIB-T TChiplet Summit 2026,Aditya Vaidya5EMIB-T PrimerCurrently in High volume:EMIBThe Future:EMIB-T(7)E