20260219_B-201_Bhargav.PDF

1、Systematic Verification Strategy for UCIePresentersKatakam Bhargav,Nagendra VarmaContents2Introduction to UCIeComplexities in UCIe.Features used in UCIeIntroduction to JESD 204EChallenges FacedVerification MethodologyTB ArchitectureApproaches usedStrategies helped in Verification Flow.Conclusion3WHA

2、T IS UCIE?Unified Chiplet CommunicationUCIe provides a standard for high-bandwidth,low-latency communication between heterogeneous chiplets across vendors.Layered ArchitectureUCIe architecture includes PHY,Adapter,and Protocol layers ensuring electrical signaling,data mapping,and integrity.Advanced

3、Packaging SupportSupports advanced packaging like 2.5D and 3D integration,emphasizing energy efficiency and reliability.Die to Die Packaging.Modular Ecosystem BenefitsStandardization accelerates SoC development,enabling modular IP block integration from multiple vendors.4WHY IS UCIE COMPLEX?Multi-La

4、yer ArchitectureUCIes multi-layer design demands precise timing and coordination for reliable link training and maintenance.Evolving PHY FeaturesSupport for quadrature clocking and configurable postamble adds timing and signaling variability.Interoperability ChallengesVendor extensions and non-stand

5、ard clock rates complicate interoperability and verification processes.Debugging and VerificationDebugging requires visibility across FDI,RDI,and PHY interfaces with modular scalable methodologies.Protocol LayerAdapter LayerPhysical LayerFlit Data Interface(FDI)Raw Data Interface(RDI)Features Used i

6、n UCIe5FeaturesPurposeWidth DegradeUCIe allows to operate on less lanes if there is an errors or corruption on lanes.Lane ReversalReversed the connection b/w Tx-Rx in each die and sePHYRETRAINRDI/FDI is requesting for Retrain if Higher layers need to do Re-Linkup.Raw FormatUcie 3.0 supports using th