20260218_E-103_Mastroianni.PDF

1、CPO:Enabling the path to I/O Density and EfficiencyTony MastroianniSenior Director 3D IC Solutions EngineeringSiemens EDAUnrestricted|Siemens 2026|Siemens Digital Industries SoftwareIndustry TrendsAI is quickly becoming the defining technology of our timesTechnical challenges are stressing the semic

2、onductor industryUnprecedented Industry,R&D and Government investmentsIntegrated Co-Packaged Optics(CPO)is a path forwardEnables reduced GPU/CPU Memory and Switch IO PowerEnables increased I/O DensityScalable to full panel level 3D IC IntegrationTechnical ChallengesCompute PerformanceMemory Capacity

3、 I/O BandwithPowerScalability Design tools and workflows3D IC Design enables the advancement of AI Hardware DesignsUnrestricted|Siemens 2026|Siemens Digital Industries SoftwareASIC/SoC with External Memory Interface Replicated Processor Core arrayExternal DDR InterfaceSerdes interfaces on N/SMaximiz

4、e(reticle)die sizeTypical Monolithic Micro-architectureASIC/SoC DiePackage SubstrateDDR SIMASIC/SOCPackage SubstrateASIC/SOCPackage SubstrateProcessor CoreProcessor CoreProcessor CoreProcessor CoreProcessor CoreProcessor CoreProcessor CoreProcessor CoreProcessor CoreProcessor CoreProcessor CoreProce

5、ssor CoreProcessor CoreProcessor CoreProcessor CoreProcessor CoreLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesLR SerdesDDR PHYDDR PHYDDR PHYDDR PHYPCBUnrestricted|Siemens 2026|Siemens Digital Industries Softwar

6、eASIC/SoC with External Memory Interface Replicated Processor Core arrayExternal DDR InterfaceSerdes interfaces on N/SMaximize(reticle)die sizeTypical Monolithic Micro-architectureASIC/SoC DiePackage SubstrateDDR SIMASIC/SOCPackage SubstrateASIC/SOCPackage SubstrateProcessor CoreProcessor CoreProces