20260219_B-202_Fung.PDF

1、Chiplet Advantages-Scaling Across Copper and OpticsSue Hung Fung Principal Product Marketing ManagerLogicI/OI/OI/OI/OI/OI/OI/OI/OHBMHBMHBMMemoryHBMMemoryMemoryMemoryBenefits and Drawbacks More logic,I/O,gates,memory,peripheral functions Limited by full-reticle size Yield reduced by large die size Si

2、ngle process node Requires complex integration of IP Design and verification time and risk Licensing cost I/O must be in the most advanced technology Every I/O must be capable of driving any interconnect Limited flexibility for multiple use-casesMonolithic SolutionsHBMLogicUCIeUCIeUCIeUCIeI/OI/OUCIe

3、UCIeHBMLogicUCIeUCIeUCIeUCIeI/OI/OUCIeLogicI/OI/OUCIeUCIeUCIeUCIeUCIeUCIeHBMMemoryLogicI/OI/OUCIeUCIeUCIeUCIeUCIeUCIeHBMMemoryMemoryMemoryChiplet-Optimized NodeAdv.Logic NodeUCIe Partition into smaller logical die I/Os disaggregated into chiplets Benefits Reuse,Reduced design time,risk,NRE and silic

4、on costs Composability,modular Independent development and validationChiplet AdvantageChiplets-Ushering a New Era of Semiconductors1https:/www.uciexpress.org/020304050601CustomChipletIO ChipletCompute ChipletOptical ChipletHigh Density Memory ChipletHigh BW Memory ChipletChipletsDATACENTER CHIPLETSW

5、ide acceptance of the Universal Chiplet Interconnect Express1(UCIe)standard in 2022 to accelerate and democratize the chipletecosystemIC design and package optimizations are the future for advanced compute semiconductorsCPUMemoryIOAcceleratorChiplets rely on a fabric of dense high-speed die-to-die i

6、nterconnectThe New Chiplet Design ParadigmThe AI Connectivity Suite-Building the Modern Data CenterPeripheral PCIe/CXLNetworking EthernetMemory HBMDie-to-Die UCIexPUxPUFront End:EthernetBack End:UltraEthernet or PCIe basedPeripheral interconnectsPCIe/CXLPCIe/UCIeHBMCPUAMBACHI C2CUALink/NVLinkAI Chip