20260218_C-103_Surana.PDF

1、Accelerated Design Closure for Integrating Chiplets on EMIB-TSatish SuranaIntel FoundryEmbedded Multi-die Interconnect Bridge-T(EMIB-T)2 EMIB-T is an advanced package using interconnect bridges with through-silicon vias(TSVs)embedded in the substrate.EMIB-T is scalable and an effective solution for

2、heterogeneous integration with mix and match of heterogeneous dies.Large farm factor packaging for AI system could be enabled by EMIB-TPackage sizes 120 mm x 180 mmNumber of bridges 38 bridgesDie to die interconnection pitch is scaling 45 umGreater than 12x reticle content could be packaged TSVs sup

3、plies power directly from the bottom of the package delivery.Minimal DC and AC noise by reducing power transmission resistance.Supports power demands of high-bandwidth memories.(HBM4 and HBM4e)Achieving data transmission rates of over 32Gb/s with UCIe-A interconnect technology.High-density Metal-Ins

4、ulator-Metal(MIM)capacitors within the bridge,Effectively suppress power noise.Reduce electromagnetic interference issues during high-speed signal transmission.Synopsys Reference Methodology for integrating chiplets on EMIB-T 3IC Validator(ICV)EMIB-T Reference Methodology with Synopsys Tools4User fl

5、ow settingsBC Factor,EOArm_setupEMIB Size&Origin Calculations TechnologyDesign InputsDesign Collaterals*3dbx/3dbv filesRef library,Tech Files,PDKTop Design Creation w/o EMIBUser update EMIB 3dbv fileDie Ring/BSB/TSV PlanningHBM/UCiE/D2D RoutingPG mesh&MIM/FILL AdditionThermal AnalysisIR/EM AnalysisF

6、unctional Verification/LVSPhysical VerificationBump Mirroring&AssignmentReports3DIC CompilerNlibs/NDMsOas of EMIBsNetlistsLogsSign-off AnalysisTop design Using 3dbloxDerive EMIB width/heightExport Bump locationsD2D Routing EMIB(s)TSV Planning placement&connections for EMIB(s)PG mesh creation&MIM/FIL