20260218_B-101_Cheruliyil.PDF

1、Speakers:Archana Cheruliyil,John CakaFrom Simulation to Silicon:System Design Methodologies for Reliable 64G UCIe Chiplet InterconnectsDie-to-Die Interconnects for Disaggregated AI Silicon2COMPUTE TO COMPUTECOMPUTE TOMEMORYCOMPUTE TOI/O FormFactorData RatesProtocolUCIe-AP/UCIe-3DUCIe-SP 32 Gbps 64 G

2、bps UCIe Streaming UCIe-APUCIe-SP 32 Gbps 64 Gbps UCIe Streaming to HBMUCIe Streaming to DDRUCIe-APUCIe-SP 32 Gbps 64 Gbps UCIe Streaming or RetimerAlphawave UCIe D2D building blocks are available today in 7nm,6nm,5nm,4nm,3nm and 2nmPackage TypeRX Term.PitchReachCompliance and Margin in VTFStandard

3、Package50Ohm110-130um25mm+Silicon InterposerOpen25-55um1-5mmRDL InterposerOpen25-55um1-5mmSilicon BridgeOpen25-45um1-5mmDieInterposerDiePHYPHYPackage SubstrateDieDiePHYPHYPackage Substrate Package SubstrateDieDiePHYPHYDieRDL InterposerDiePHYPHYPackage SubstrateUCIe Channels Designed for Universal Pe

4、rformanceAlphawave UCIe-Advanced Package Simulation to Silicon D2D Link 2D Eye PlotBoard SetupDriving Innovation with the Right PerformanceCost EquationOrganic InterposerSilicon BridgeSilicon InterposerSil2SimScalable ArchitectureInnovative Package Routing to Reduce CrosstalkSilicon to Simulation Co

5、rrelationEnabling Best-in-Class 64G UCIe IPAlphawave UCIe-Standard Package Simulation to Silicon Delivering Proven Silicon Success Alphawave UCIe Silicon Proven Roadmap Gen1 24 GbpsGen2 36 GbpsGen3 64 GbpsSilicon-proven UCIe on Standard Package and Advanced CoWoSAvailable in Multiple Technology node

6、s3rdGenArchitecture UCIe Standard and Advanced PackageReliable Die-to-Die LinksGPUDomain specific language (eg.CUDA)NVIDIA H10080GB HBM33TB/S Memory BW900GB/S NV-Link4MONOLITHIC GPU700W80B Transistors814mm212 CHIPLETS700W153B TransistorsAMD MI300X192GB HBM35.2TB/S Memory BW896GB/S Infinity Fabric BW