BoW 2.1 新应用增强功能.pdf

1、BoW 2.1 Enhancements for New ApplicationsBoW 2.1 Enhancements for New Applications Kevin Donnelly,Eliyan CorporationAnu Ramamurthy,Microchip TechnologyMorgan Whately,Infineon TechnologiesSERVER:OPEN CHIPLETECONOMYOCP Open Chiplet Economy(OCE)BoW provides open PHY and Link Layer specifications standa

2、rdized under OCP,enabling D2D interfaces to be optimized to their host chiplet productsThe BoW ecosystem has broad industry adoption with known PHY implementations in 65nm,22nm,16nm,12nm,7nm,6nm,5nm,4nm,3nmRecent focus of the BoW workstream has been on a 2.1 spec extension that enable additional chi

3、plet products/product categories:BoW Memory Adding dynamic bidirectional/mixed direction slices for memory chipletsBoW FlexI SDR,streamlined PHY for cost-sensitive and/or ultra-wide applications BoW Optical Common set of recommended configurations for optical chipletsBoW 2.1 Memory spec is the first

4、 of these extensions to be published Bunch of Wires(BoW)PHY Workstreamhttps:/www.opencompute.org/documents/bow-memory-addendum-final-pdfThe”Memory Wall”is limiting the performance of Generative AI ASICsThe top factor driving recent performance increases is due to DRAM bandwidth boostsDriving factor

5、is BW/mm metric on ASIC edges(beachfront)D2D interfaces have the potential to dramatically improve memory BW/mm for ASICsBoW Memory:Extensions to BoW for MemoryThe purpose of BoW 2.1 for Memory is to provide optional enhancements that enable BoW to be more efficiently used to directly connect memory

6、 devices to ASICs.BoW Memory:D2D PHY Signaling TerminologyMost D2D PHY specs use fixed unidirectional signalingBoW 2.0 allows for bidirectional PHYs,but configured as fixed unidirectionalBoW 2.1 enables half-duplex signaling(like all memory PHYS)BoWEx:UCIeFull-Duplex/2 WiresEx:BoW 2.0Full-Duplex/2 W