33-d3s5-2-RISC-V Summit China 2023 - RISC-V Vector Support on Valgrind.pdf

1、RISC-V Vector Support on ValgrindWu Fei System Software ArchitectLegal Notices and DisclaimersBackgroundValgrind currently lacks support for the RISC-V Vector ISA,while it has already been enabled for RV64GC.There is no existing support on Valgrind for variable length vector instructions,a new desig

2、n is required.Here is a simplified flow of how Valgrind works:InstrumentationMemcheckGuestInstructionHostInstructionIRDesign Choices The preferred way in descending order to enable new instruction on Valgrind Using existing Iops,creating new Iops,clean helper,dirty helperMethod for RVVProConsScalar

3、emulationLeverage existing scalar IRsIR explosionHard to optimizeDirty helperEasy for basic binary translation,e.g.tool=noneDeviate from the design principle of ValgrindDeal with the instrumentation tools such as Memcheck directlyVector IRStandard way to extend IRGeneric design across different vect

4、or ISAsRequires brand new designChallengesGeneric framework and IRs for different vector ISARVV LMUL and backend register allocation No register group allocation yetMask instruction efficiency Inefficient to handle it element by element Current StatusA generic vector IR encoding mechanismA working p

5、rototype to run simple RVV testcases A few instructions uses the new vector IR Memcheck runs well on the prototype Framework enhancement such as adding CPU state to TBThe Vector IR design is still in reviewRVV Intel public repository:https:/ repository:https:/ StepGet the vector IR design reviewedDe

6、sign the code pattern for common features such as LMUL,maskComplete the full RVV supportRISE is focused on positive and transparent collaborations with upstream projects to deliver commercial-ready software for various use casesGoal:Acceler